There is an information processing apparatus including a central processing unit (CPU) and a field programmable gate array (FPGA) capable of changing a configuration of a programmable logic circuit, and executing, with the use of the FPGA, processing suitable for processing by hardware. For example, an FPGA accelerator is used for realizing speed-up of data processing such as data search processing. Processing by the CPU is limited to parallel processing in accordance with the number of cores, but, processing by the FPGA enables speed-up of processing through pipelining or parallel processing so far as a circuit resource permits. However, as the FPGA becomes higher performance by increasing the number of stages of pipeline or increasing a degree of parallel processing, the number of arithmetic units or the number of flip-flops increases, resulting in that a circuit area increases.
There is an FPGA which enables a dynamic partial reconfiguration in which it is possible to partially change a configuration of a programmable logic circuit without stopping an operation of a logic circuit in operation (refer to Patent Document 1, for example). The FPGA enabling the dynamic partial reconfiguration can execute a plurality of tasks in an asynchronous manner with the use of one FPGA, by arranging a circuit related to a task to be newly executed in a space area, through the dynamic partial reconfiguration, without stopping another task in execution.
For example, when execution of a task A is requested in an initial state 1101 in which a circuit arrangement is not performed on any of a plurality of programmable areas as illustrated in FIG. 11A, a circuit 1102 related to the task A is arranged as exemplified in FIG. 11B, through a dynamic partial reconfiguration, to execute the task A. When, during the execution of the task A, execution of another task B is requested, a circuit 1103 related to the task B is arranged as exemplified in FIG. 11C, through a dynamic partial reconfiguration, to execute the task B. When execution of another task C is further requested, a circuit 1104 related to the task C is arranged as exemplified in FIG. 11D, through a dynamic partial reconfiguration, to execute the task C.
After that, when the task B is terminated, the area used for the task B is set to a space area, as illustrated in FIG. 11E. When, in the state illustrated in FIG. 11E, execution of another task D is requested during the execution of the task A and the task C, a circuit 1105 related to the task D is arranged as exemplified in FIG. 11F, through a dynamic partial reconfiguration, to execute the task D. In a manner as described above, the FPGA enabling the dynamic partial reconfiguration can execute a plurality of tasks in an asynchronous manner with the use of one FPGA.
There is proposed an image forming apparatus in which, when performing concurrent processing of processing a plurality of types of jobs in a concurrent manner, an assigned amount of a shared resource such as a memory or a disk for each job during execution of job, is dynamically changed to be allocated so as to correspond to a priority order of the job (refer to Patent Document 2, for example). There is proposed a computer system in which, when assigning a logical processor to a new process, the logical processor is assigned so as to bring out a performance of a physical processor in accordance with a dependency relation between the process and a process to which a logical processor is already assigned, to thereby perform resource assignment which is optimum for execution of a program (refer to Patent Document 3, for example).
Patent Document 1: Japanese Laid-open Patent Publication No. 2015-191335
Patent Document 2: Japanese Laid-open Patent Publication No. 11-205493
Patent Document 3: Japanese Laid-open Patent Publication No. 2006-24180
When an FPGA accelerator is used, even in a case of tasks using the same accelerator circuit, processing amounts in the accelerator with respect to a processing amount of all of the tasks are not always the same. For this reason, an influence exerted on a processing time of the task by a performance of the accelerator is different depending on the tasks. Therefore, in order to improve a processing performance in the entire information processing apparatus, there is a need to properly assign a circuit resource of the FPGA to a task to be executed.
However, when a programmable area has an extra area in an FPGA enabling a dynamic partial reconfiguration, a circuit with high performance and large area is arranged, among a plurality of circuit configurations with different processing performances, resulting in that a circuit resource of the FPGA may be unnecessarily consumed. As a result of this, a circuit resource of the FPGA capable of being used by a succeeding task is reduced, and a throughput of the entire information processing apparatus is sometimes deteriorated.